This application claims the benefit of Korean Application No. 2000-46615, filed Aug. 11, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to integrated circuit memory devices, and more particularly, to protective structures for dielectric regions, such as capacitor dielectrics, and methods for fabricating the same.
As the integration density of integrated circuit memory devices increases, there are typically decreases in, for example, the area of memory cells in the device. Decreasing the area of memory cells in the device may reduce the capacitance of capacitors in such devices. To increase the effective area of a three-dimensional capacitor on a substrate a thin dielectric layer may be interposed between upper and lower electrodes of a capacitor. The dielectric layer preferably comprises a material having high dielectric constant. However, manufacturing processes associated with forming such capacitors may be complex and relatively expensive. In addition, Fowler-Nordheim currents may cause decreased reliability of resultant devices if the thickness of the dielectric layer is smaller than, for example, 100 xc3x85.
These problems have made the use of high dielectric constant ferroelectric substances an attractive choice for the dielectric layer of capacitors in integrated circuit memory devices. Like ferromagnetic substances, ferroelectric substances have a hysteresis characteristic in which a remnant polarization value changes under a given electric field. Thus, ferroelectric substances can have a remnant polarization (Pr) even in the absence of an external electric field. One important parameter in determining the operating voltage of a device can be referred to as a coercive electric field. The coercive electric field is present when the external electric field causes the value of the remnant polarization (Pr) to be 0. The remnant polarization (Pr) makes reading and writing possible in, for example, ferroelectric RAM (FRAM) devices.
However, when the dielectric layer of the capacitor comprises a ferroelectric material, the dielectric characteristic of the dielectric layer can be degraded during manufacturing of integrated circuit memory devices. For example, after the capacitor is be formed, an interlayer dielectric (ILD) process, an intermetal dielectric (IMD) process and a passivation process may be performed. In performing these processes, chemical vapor deposition (CVD) and/or plasma enhanced CVD (PE-CVD) deposition processes can be used in which hydrogen gas and/or silane (SiH4) gases are used as a carrier gas. However, when carrier gases such as these are used, the gas can directly react with oxygen present in the ferroelectric material, such as Pb(ZrTi)O3 and/or SrBi2Ta2O9, to yield water (H2O). As a result, the ferroelectric material may lack oxygen which can degrade electrical characteristics of the ferroelectric material.
To solve this problem, a method of encapsulating a capacitor with a single insulation layer has been used. For example, U.S. Pat. No. 5,822,175 discloses a method of encapsulating a capacitor with a silicon oxide layer, a doped silicon nitride layer and a silicon nitride layer to reduce degradation of the dielectric layer. To enhance the insulation properties of the dielectric layer, an annealing process can be performed in an oxygen atmosphere at a temperature of 600-800xc2x0 C. Unfortunately, hydrogen can be generated when an encapsulating layer is formed. This hydrogen may diffuse into the dielectric layer. Moreover, the diffusion of hydrogen can be accelerated during the succeeding annealing process.
In some embodiments of the present invention, a memory device includes a capacitor comprising a lower electrode, an upper electrode and a dielectric layer interposed between the lower electrode and the upper electrode. A multi-layered encapsulating layer surrounds the capacitor, the multi-layered encapsulating layer comprising a first blocking layer, e.g., a first metallic oxide layer, which is annealed and a first protection layer, e.g., a second metallic oxide layer, formed on the surface of the annealed first blocking layer, the first blocking layer and the protection layer being formed of the same material. Preferably, the first blocking layer has a thickness sufficient to block diffusion of hydrogen generated during the formation of the first protection layer.
In other embodiments of the present invention, a memory device comprises a lower electrode, a dielectric layer formed on a predetermined portion of the surface of the lower electrode, and a spacer layer formed on the lower electrode, the spacer layer comprising a blocking spacer directly contacting each sidewall of the dielectric layer and a protection spacer formed on the blocking spacer. An interlayer insulation layer is formed on the lower electrode to contact the protection spacer and an upper electrode is formed on the dielectric layer. A multi-layered encapsulating layer surrounds the interlayer insulation layer, the spacer layer and the upper electrode, the multi-layered encapsulating layer comprising a first blocking layer which is annealed and a first protection layer formed on the surface of the annealed first blocking layer, the first blocking layer and the protection layer being formed of the same material, e.g., a metal oxide.
In still other embodiments of the present invention, an integrated circuit comprises a ferroelectric dielectric region on a substrate, a first metal oxide layer directly on a surface of the ferroelectric dielectric region, and a second metal oxide layer on the first metal oxide layer. The first metal oxide layer is configured to enable a remnant polarization of the ferroelectric dielectric region to increase during an annealing of the substrate before formation of the second metal oxide layer. The first metal oxide layer preferably is thick enough to substantially impede diffusion of hydrogen into the ferroelectric dielectric region in, for example, subsequent fabrication operations. The first metal oxide layer may comprise a metal oxide selected from the group consisting of Al2O3, TiO2, ZrO2, Ta2O5 and CeO2. Similarly, the second metal oxide layer may comprise a metal oxide selected from the group consisting of Al2O3, TiO2, ZrO2, Ta2O5 and CeO2. The first and second metal oxide layers may be formed from the same material. In embodiments of the invention, the second metal oxide layer is thicker than the first metal oxide layer. For example, the first and second metal oxide layers may comprise respective first and second metal oxide layers, with the second metal oxide layer being at least about twice as thick as the first metal oxide layer, and less than about ten times thicker than the first metal oxide layer.
In method embodiments of the present invention, a memory device is fabricated. A capacitor is formed on a semiconductor substrate, the capacitor comprising a lower electrode, an upper electrode and a dielectric layer interposed between the lower electrode and the upper electrode. A multi-layered encapsulating layer is formed to surround the capacitor, the multi-layered encapsulating layer comprising a first blocking layer which is annealed and a first protection layer formed on the surface of the first blocking layer, the first blocking layer and the protection layer being formed of the same material. Preferably, the first blocking layer is formed to have an enough thickness to block diffusion of hydrogen generated during the formation of the first protection layer.
According to other method embodiments of the present invention, a protective structure for a ferroelectric dielectric region on an integrated circuit substrate is formed by depositing a first metal oxide layer directly on a surface of the ferroelectric dielectric region. The first metal oxide layer and the ferroelectric dielectric region are then annealed. A second metal oxide layer is then formed on the first metal oxide layer. Preferably, the first metal oxide layer is sufficiently thin enough to enable a remnant polarization of the ferroelectric dielectric region to increase during the annealing of the first metal oxide layer and the ferroelectric dielectric region, and sufficiently thick enough to reduce diffusion of hydrogen into the dielectric region during the depositing of the second metal oxide layer.